Home > Verimag > Jobs and Internships

[master/PhD] Static analysis of “pseudo-LRU” caches

The naive vision of cache memory is that it stores “the most recently accessed data”. In reality, each memory block can be stored in one specific part of the cache memory (the cache set suitable for the block’s address), and furthermore the block evicted from the cache set is not necessarily the least recently used (LRU). In fact, many processors implement “pseudo-LRU” policies cheaper to implement in hardware and that have similar practical performance. For safety-critical hard real time applications, it is necessary to prove bounds on the worst-case execution time (WCET). For this, it is necessary to know which accesses are cache hits or misses. There are several good analyses, including “exact” ones, for LRU caches in the scientific literature. There are no such good analyses for pseudo-LRU policies. In fact, it can be shown that static analysis for pseudo-LRU policies belongs to higher complexity classes than for LRU. The topic of the internship (possibly leading to a thesis) is to research good and practically efficient analysis for pseudo-LRU policies.


New publications

Jobs and internships

Contact | Site Map | Site powered by SPIP 4.2.16 + AHUNTSIC [CC License]

info visites 4214819