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Postdocs
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
PhD Thesis
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
Jobs in the whole Verimag lab
New publications
Some Recent Publications (Ressources Partagées)
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Jobs and internships
Jobs and internships (Ressources Partagées)
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
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