Accueil
>
Verimag
>
Projets
Model-based Testing for Embedded Systems
Bosch, 2015-2016
Project funded by Bosch, Stuttgart, Germany
Investigator : Thao Dang
Navigation
Rubriques
Verimag
Membres
Publications
Outils
Thèse en cours
Emplois et stages
Projets
Partenaires
Colloques et Conférences
Séminaires
Documents
Axes
Contact
Plan du site
Acces au Batiment
Actualités
ACTUALITÉS
Junior professorship chair on verifiable / explainable artificial intelligence
Poste de professeur des universités (section 27)
Séminaires
Séminaires
4 avril 2024
Sébastien Michelland:
Abstract interpreters: a monadic approach to modular verification
11 avril 2024
Andrei Paskevich:
Coma: an intermediate verification language with explicit abstraction barriers
2 mai 2024
Matthieu Moy:
How to build a broken system?
Nouvelles publications
Quelques Publications Récentes
Aina Rasoldier, Jacques Combaz, Alain Girault, Kevin Marquet, Sophie Quinton:
Assessing the Potential of Carpooling for Reducing Vehicle Kilometers Traveled
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Marius Bozga, Radu Iosif, Joseph Sifakis:
Verification of component-based systems with recursive architectures
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Offres d'emploi et stages
Offres d'emploi et stages
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Bourses PERSYVAL de M2
Junior professorship chair on verifiable / explainable artificial intelligence
Poste de professeur des universités (section 27)
[Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
[Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
[Funded PhD] Quantitative analysis of software security against adaptive attacks
[Master] A Solver for Monadic Second Order Logic of Graphs of Bounded Tree-width
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
[Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Contact
|
Plan du site
|
Site réalisé avec SPIP 4.2.8
+
AHUNTSIC
[CC License]
info visites
3901818
English
Français