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Emplois et stages
Postdocs
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
Emplois et stages à Verimag
Nouvelles publications
Quelques Publications Récentes (Ressources Partagées)
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Offres d'emploi et stages
Offres d'emploi et stages (Ressources Partagées)
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
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