@mastersthesis{Bou07a, 
    title = { Acc\'el\'eration des simulations de syst\`emes sur puce au niveau transactionnel  }, 
    author = {Bouzouzou, Yussef},
    year = {2007},
    type = {Dipl\^ome de Recherche Technologique},
    school = {Universit\'e Joseph Fourier},
    team = {SYNC},
}
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      - 13 novembre 2025 Yann Herklotz: Towards scalable verification and efficient hardware generation using verified (…)
- 21 novembre 2025 Oussama Oulkaid: Formal models of integrated circuits for transistor level electrical verification (Phd)
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- 1er décembre 2025 Sylvain Boulme: Introduction à la programmation orientée objet en crystal
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   - Basile Pesin, Sylvain Boulmé, David Monniaux, Marie-Laure Potet: Formally Verified Hardening of C Programs against Hardware Fault Injection
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian: Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs
- Marius Bozga, Radu Iosif, Florian Zuleger: Regular Grammars for Sets of Graphs of Tree-Width 2
- David Monniaux, Sylvain Boulmé: Chamois: agile development of CompCert extensions for optimization and security
 
Offres d'emploi et stages
-   Offres d'emploi et stages  
 - [Funded PhD] Fault Injection Attacks : Automated Analysis of Counter-Measures At The Binary Level
- [Master] Decision Procedure for Equivalence Relations
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
 
 
    
   