Accueil
>
Verimag
>
Thèse en cours
>
Thèse en cours
Thèse en cours
Thomas Mari
(2019 - 2024)
Aina Rasoldier
(2020 - 2024)
Ihab Alshaer
(2020 - 2024)
Thomas Vigouroux
(2021 - 2024)
Lucas Bueri
(2021 - 2024)
Bob Aubouin-Pairault
(2021 - 2024)
Hadi Dayekh
(2021 - 2024)
Alban Reynaud Michez
(2022 - 2025)
Oussama Oulkaid
(2022 - 2025)
Ana Maria Gomez Ruiz
(2022 - 2025)
Weicheng He
(2023 - 2026)
Benjamin Bonneau
(2023 - 2026)
Alexandre Berard
(2023 - 2026)
Baptiste De Goër De Herve
(2023 - 2026)
Basile Gros
(2023 - 2026)
Actualités
ACTUALITÉS
Junior professorship chair on verifiable / explainable artificial intelligence
Séminaires
Séminaires
2 mai 2024
Matthieu Moy:
How to build a broken system?
30 mai 2024
Mohamed Maghenem:
A hybrid-systems framework for distributed gradient-based estimation
Nouvelles publications
Quelques Publications Récentes
Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard:
Formally Verifying Optimizations with Block Simulations
Dominique Larchey-Wendling, Jean-François Monin:
Proof Pearl: Faithful Computation and Extraction of \mu-Recursive Algorithms in Coq
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
David Monniaux, Léo Gourdin, Sylvain Boulmé, Olivier Lebeltel:
Testing a Formally Verified Compiler
Offres d'emploi et stages
Offres d'emploi et stages
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Bourses PERSYVAL de M2
Junior professorship chair on verifiable / explainable artificial intelligence
[Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
[Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
[Funded PhD] Quantitative analysis of software security against adaptive attacks
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
[Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Navigation
Rubriques
Verimag
Membres
Publications
Outils
Thèse en cours
Emplois et stages
Projets
Partenaires
Colloques et Conférences
Séminaires
Documents
Axes
Contact
Plan du site
Acces au Batiment
Contact
|
Plan du site
|
Site réalisé avec SPIP 4.2.8
+
AHUNTSIC
[CC License]
info visites
3954386
English
Français