Verimag

News

New publications

• Some Recent Publications
  • Karine Altisen, Pierre Corbineau, Stéphane Devismes: Certification of an exact worst-case self-stabilization time
  • Sylvain Boulmé: Construire des logiciels fiables
  • Claire Maiza: Hardware and software analyses for precise and efficient timing analysis
  • David Monniaux, Léo Gourdin, Sylvain Boulmé, Olivier Lebeltel: Testing a Formally Verified Compiler

Jobs and internships

• Jobs and internships
  • [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
  • [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
  • [Funded PhD] Quantitative analysis of software security against adaptive attacks
  • [Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
  • [Master] Analyzing fault parameters triggering timing anomalies
  • [Master] Exploration by model-checking of timing anomaly cancellation in a processor
  • [Master] Towards New Frontiers in Multi-Core Response Time Analysis?
  • [Master]Leakage in presence of an active and adaptive adversary
  • [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences

Sections

• Verimag
  • Members
  • Publications
  • Tools
  • Ongoing Phd Thesis
  • Jobs and Internships
  • Projects
  • Partners
  • Workshops and Conferences
  • Seminars
  • Documents
• Topics
• Contact
• Site Map

---

• Building Access