Home > Verimag > Partners > Partners
Partners
Current Collaborations
Academic partners
- CEA Saclay : TAVA
- CEA/LIST : CAOTIC: Collaborative Action on Timing Interferences
- INRIA/Kairos : CAOTIC: Collaborative Action on Timing Interferences
- IRISA : CAOTIC: Collaborative Action on Timing Interferences
- IRIT : CAOTIC: Collaborative Action on Timing Interferences
- IRIT/MACAO : IF Toolset
- LCTI : CAOTIC: Collaborative Action on Timing Interferences
- LS2N : CAOTIC: Collaborative Action on Timing Interferences
Industrial partners
- Amossys : TAVA
- Argosim: Coopération Argosim
- IRT : CAOTIC: Collaborative Action on Timing Interferences
- PragmaDev, Paris, France : Cooperation PragmaDev
Past Collaborations (<8 years)
Past Academic partners
- CEA Saclay: VECOLIB
- CEA/LETI, Grenoble, France: ARAMIS , BINSEC , BRAIN-IoT , IoIT
- CITI: Funded Ph.D: Dynamic Memory Management For Embedded Non-Volatile Memory
- CRAN: COMPACS
- DFKI - German Research Center for Artificial Intelligence, Germany: ADE , ESROCOS
- DLR - German Aerospace Center, Germany: ESROCOS
- Eindhoven University of Technology, The Netherlands: CITADEL
- Fondazione Bruno Kessler, Trento, Italy: CITADEL
- GIPSA-Lab: SACADE
- INRIA/Gallium: VOCaL (The Verified OCaml Library)
- INRIA/POLARIS: CASERM
- INRIA/SPADES: CASERM
- INRIA/Tamis: SUCCESS
- IRIT/MACAO: Moc4Space
- ISAE SUPAERO, Toulouse, France: ESROCOS
- Joanneum Research Forschungsgesellschaft, Austria : ADE
- Katholieke Universiteit Leuven, Belgium: ESROCOS
- King’s College London, UK: ADE , ERGO
- LAAS, Toulouse, France: SAFENAV
- LaBRI: ESTATE
- LCIS Valence: CLAM
- LIAFA/Modelisation et Verification: VECOLIB
- LIG/Drakkar: IoIT
- LIG/Vasco: SACADE
- LIG–EHCI: IoIT
- Links Foundation, Turin, Italy: BRAIN-IoT
- LIP6: ESTATE
- LJK: COMPACS
- LORIA: BINSEC
- LRI Orsay / INRIA: VOCaL (The Verified OCaml Library)
- Middlesex University London, UK: SUCCESS
- The Chancellor, Masters and Scholars of the University of Oxford, UK: ADE
- TIMA, Grenoble, France: CLAM
- Universidad de Malaga, Spain: ADE
- Universita del Salento, Italy : ADE
- Universität Basel, Switzerland: ERGO
- University of Twente, The Netherlands: SUCCESS
- VTT - Technical Research Centre, Finland: ESROCOS
Past Industrial Partners
- AdaCore: VECOLIB
- Airbus Defence and Space, UK: ADE , ERGO , ESROCOS
- Airbus Hélicoptères: Airbus Helicopters
- Atos Origin: ARAMIS
- atsec information security AB, Stokholm, Sweden: CITADEL
- Cassidian Cybersecurity SAS - Airbus, France: BRAIN-IoT
- EADS/Innovation Works (France): BINSEC
- Ellidiss Technologies, France: ERGO
- Empresa Municipal de Aguas de la Coruna SA, Spain: BRAIN-IoT
- eVaderis: Funded Ph.D: Dynamic Memory Management For Embedded Non-Volatile Memory
- Frequentis, Wien, Austria: CITADEL
- GMV Innovating Solutions, Spain: ADE , ERGO , ESROCOS , Moc4Space
- IDATE, France: BRAIN-IoT
- IK4-IKERLAN, Spain: CITADEL
- Institut fur angewandte Systemtechnik Bremen GmbH, Germany: CITADEL
- Intermodalics, Leuven, Belgium: ESROCOS
- J.W. Ostendorf GmbH & Co. KG, Germany: CITADEL
- Kalray, Grenoble, France: Kalray , KALRAY , KALRAY-CompCert , Matheus Schuh , the Chamois CompCert Compiler
- Kaspersky Lab UK Ltd, UK: CITADEL
- MathWorks: [master or PhD] Convex polyhedra in floating point
- OAS AG, Germany: CITADEL
- OCamlPro: VOCaL (The Verified OCaml Library)
- Paremus Ltd, UK: BRAIN-IoT
- Robotnik Automation SLL, Spain: BRAIN-IoT
- SciSys, UK: ERGO
- Siemens Aktiengesellschaft, Germany: BRAIN-IoT
- Siotic Spain SL - Improving Metrics, Spain: BRAIN-IoT
- Steery.io, France: SAFENAV
- STMicroelectronics/Grenoble: BRAIN-IoT , Certified compilation for security , Potential CIFRE PhD: Hardened circuits for critical applications , STMicroelectronics , STMicroelectronics , Thèse CIFRE : Cybersecurity - Fault injection attacks , Variabilité des Circuits Analogiques Hiérarchiques (NANO 2017)
- SYSGO, Germany: CITADEL
- Thales Alenia Space Italia SPA, Italy: ADE
- The Open Group, UK: CITADEL
- TRASYS International Geie, Belgium: ADE
- TrustInSoft: VOCaL (The Verified OCaml Library)
- TTTech Computertechnik, Wien, Austria: CITADEL
- UniControls, Prague, Czech Republic: CITADEL
- UTRC, Ireland: Test Generation for Simulink Models
Verimag is member of the SCADE Academic Program
