@phdthesis{Moy14a,
title = { High-level Models for Embedded Systems },
author = {Moy, Matthieu},
year = {2014},
address = {Verimag},
type = {Habilitation \`a Diriger des Recherches ({HDR})},
school = {Univ. Grenoble Alpes, VERIMAG, F-38000 Grenoble, France},
team = {SYNC},
}
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- Some Recent Publications
- Claire Maiza: Hardware and software analyses for precise and efficient timing analysis
- Aina Rasoldier, Jacques Combaz, Alain Girault, Kevin Marquet, Sophie Quinton: Assessing the Potential of Carpooling for Reducing Vehicle Kilometers Traveled
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing Synchronous Unison in Directed Networks
- Marius Bozga, Radu Iosif, Joseph Sifakis: Verification of component-based systems with recursive architectures
Jobs and internships
- Jobs and internships
- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- PERSYVAL Master 2 Scholarships
- Junior professorship chair on verifiable / explainable artificial intelligence
- Poste de professeur des universités (section 27)
- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences