CIFRE STMicroelectronics Grenoble, 2018-2021

Collaboration with STMicroelectronics, Grenoble

The “main feature” of a transaction-level (TL) model is to simulate accurately the execution of an embedded software on a given hardware. Nowadays, this feature is complemented by “diagnosis” features. For instance, if the embedded software programs invalid values or values that would cause an invalid usage of a given hardware block, an error message is reported.

We foresee the need to extend the scope of these diagnosis to other areas such as: performance, low-power, safety. The general idea is that a TL model can be used to report about improper or sub-optimal usages of the hardware, based on the intention of the SoC architect. For instance, a TL model could report that a given software is doing a memory transfer “manually” instead of actually delegating the task to a low-power DMA and putting the CPU in sleep mode. More generally, it would be interesting to quantify to which extent the software achieves the best possible usage of the given hardware for a given criteria (energy efficiency, feature coverage, etc.).

  • PhD Student: Vincent Morice
  • Supervisor: Florence Maraninchi
  • STMicroelectronics: Jérôme Cornet

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